The present invention relates to a power-source controller for reducing the current consumption when a DRAM is standby.
In general, when a DRAM is standby, /RAS and /CAS which are external clock signals are fixed to H-level and bit lines are equalized and a data bus and peripheral circuit are initialized. Main circuits consuming a current when the DRAM is standby are a word-line-voltage step-up circuit and a back-bias step-down circuit. When it is detected by a sensor the word-line voltage and back bias respectively become lower than a certain value even under a standby state, they are pumped by an oscillator and their set values are held. Therefore, current is always consumed by the sensor and pumping even under a standby state. Moreover, when a word line and a bit line are short-circuited in a memory cell by a process defect, a current is always consumed between a power source (VCC) and the GND (VSS).
As the demand of a DRAM for a portable unit rises, less current consumption is requested. However, in the case of the prior art, there is only a method for lowering a power-source voltage in order to reduce the current consumption under a standby state. In the case of this method, control by an actual unit is very complex.
A power-source controller of an DRAM of the present invention is provided with power-source-voltage control means for supplying the voltage of an external power source as that of an internal power source when detecting the enable state of the DRAM and supplying a voltage lower than the voltage of the external power source to the internal power source when detecting the disable state of the DRAM.
Moreover, a DRAM power-source controller of the present invention is provided with power-source-voltage control means for supplying the voltage of an external power source as that of an internal power source when detecting the enable state of the DRAM and setting the internal power source to the ground level when detecting the disable state of the DRAM.